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December 2006
HYI25 DC 51216 0 C E HYI25 DC 51280 0 C E
5 1 2 - M b i t D o u b l e - D a t a - R a t e SD R A M Green Product DDR SDRAM
Preliminary
Internet Data Sheet
Rev. 0.7
Preliminary Internet Data Sheet
HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
HYI25DC512160CE, HYI25DC512800CE Revision History: 2006-12, Rev. 0.7 Page All All Subjects (major changes since last revision) Qimonda template update Adapted internet edition
Previous Revision: 2006-07, Rev. 0.6
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 11292006-TAIE-H645
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Preliminary Internet Data Sheet
HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main characteristics.
1.1
Features
* Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS * Burst Lengths: 2, 4, or 8 * CAS Latency: 2, 2.5, 3 * Auto Precharge option for each burst access * Auto Refresh and Self Refresh Modes * RAS-lockout supported tRAP = tRCD * 7.8 s Maximum Average Periodic Refresh Interval * 2.5 V (SSTL_2 compatible) I/O * VDDQ = 2.5 V 0.2 V * VDD = 2.5 V 0.2 V * PG-TSOPII-66 package * RoHS Compliant Products
* Double data rate architecture: two data transfers per clock cycle * Industrial operating temperature range: -40C to +85C * Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver * DQS is edge-aligned with data for reads and is centeraligned with data for writes * Differential clock inputs (CK and CK) * Four internal banks for concurrent operation * Data mask (DM) for write data * DLL aligns DQ and DQS transitions with CK transitions
TABLE 1
Performance
Part Number Speed Code Speed Grade Max. Clock Frequency Component @CL3 @CL2.5 @CL2 -5 DDR400B -6 DDR333 166 166 133 Unit -- MHz MHz MHz
fCK3 fCK2.5 fCK2
200 166 133
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
1.2
Description
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the Industry Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
The 512-Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The 512-Mbit Double-Data-Rate SDRAM uses a doubledata-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512-Mbit Double-Data-Rate SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. The 512-Mbit Double-Data-Rate SDRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.
TABLE 2
Ordering Information for RoHS Compliant Products
Part Number HYI25DC512800CE-5 HYI25DC512160CE-5 HYI25DC512800CE-6 HYI25DC512160CE-6 Org. CAS-RCD-RP Latencies x8 x16 x8 x16 2.5-3-3 166 2-3-3 133 DDR333 3-3-3 Clock CAS-RCD-RP (MHz) Latencies 200 2.5-3-3 Clock Speed (MHz) 166 DDR400B Package PG-TSOPII-66 Note
1)
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Preliminary Internet Data Sheet
HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
2
Chip Configuration
The chip configuration of a DDR SDRAM is listed by function in Table 3. The abbreviations used in the Pin#/Buffer# column are explained in Table 4 and Table 5 respectively. The chip numbering for TSOP is depicted in Figure 1 .
TABLE 3
Chip Configuration of DDR SDRAM
Ball#/Pin# Clock Signals 45 46 44 Control Signals 23 22 21 24 26 27 29 30 31 32 35 36 37 38 39 40 28 41 42 RAS CAS WE CS BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 NC 17 A13 NC I I I I I I I I I I I I I I I I I I I I NC I NC SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL -- Address Signal 12 Note: Module based on 256 Mbit or larger dies Note: Module based on 128 Mbit or smaller dies Address Signal 13 Note: 1 Gbit based module Note: Module based on 512 Mbit or smaller dies Address Bus 11:0 Row Address Strobe Column Address Strobe Write Enable Chip Select Bank Address Bus 2:0 CK CK CKE I I I SSTL SSTL SSTL Clock Signal Complementary Clock Signal Clock Enable Name Pin Type Buffer Type Function
Address Signals
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
Ball#/Pin#
Name
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I AI PWR PWR
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- -- --
Function
Data Signals x8 Organization 2 5 8 11 56 59 62 65 51 47 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 51 16 47 20 Power Supplies 49 1, 18, 33 VREF VDD I/O Reference Voltage I/O Driver Power Supply Power Supply 3, 9, 15, 55, 61 VDDQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQS LDQS UDM LDM Data Signal Bus 7:0
Data Strobe x8 Organization Data Strobe Data Mask Data Signal 15:0 Data Mask x8 Organization Data Signals x16 Organization
Data Strobe x16 Organization Data Strobe Upper Byte Data Strobe Lower Byte Data Mask Upper Byte Data Mask Lower Byte
Data Mask x16 Organization
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
Ball#/Pin#
Name
Pin Type PWR PWR NC
Buffer Type -- -- --
Function Power Supply Power Supply Not Connected
6, 12, 52, 58, 64 VSSQ 34 VSS
Not Connected x8 Organization 4, 7, 10, 13, 14, NC 16, 17, 19, 20, 25, 43, 50, 53, 54, 57, 60, 63 14, 17, 19, 25, 42, 43, 50, 53 NC
Not Connected x16 Organization NC -- Not Connected
TABLE 4
Abbreviations for Pin Type
Abbreviation I O I/O AI PWR GND NC Description Standard input-only pin. Digital levels Output. Digital levels I/O is a bidirectional input/output signal Input. Analog levels Power Ground Not Connected
TABLE 5
Abbreviations for Buffer Type
Abbreviation SSTL LV-CMOS CMOS OD Description Serial Stub Terminalted Logic (SSTL2) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
FIGURE 1
Chip Configuration PG-TSOPII-66
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
3
Functional Description
The 512-Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The 512-Mbit Double-Data-Rate SDRAM is internally configured as a quad-bank DRAM. The 512-Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The doubledata-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512-Mbit Double-Data-Rate SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
TABLE 6
Mode Register Definition
Field BL Bits [2:0] Type1) W Description Burst Length Number of sequential bits per DQ related to one read/write command. Note: All other bit combinations are RESERVED. 001B 2 010B 4 011B 8 BT 3 Burst Type See Table 7 for internal address sequence of low order address bits. 0 Sequential 1 Interleaved CAS Latency Number of full clocks from read command to first data valid window. Note: All other bit combinations are RESERVED. 010B 011B 110B 101B Note: MODE [12:7] 2 3 2.5 1.5 CL = 1.5 for DDR200 components only
CL
[6:4]
Operating Mode Note: All other bit combinations are RESERVED. 000000 Normal Operation without DLL Reset 000010 Normal Operation with DLL Reset
1) W = write only register bit
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
TABLE 7
Burst Definition
Burst Length Starting Column Address A2 2 4 -- -- -- -- -- -- 8 0 0 0 0 1 1 1 1 Notes 1. 2. 3. 4. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. A1 -- -- 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Order of Accesses Within a Burst Type = Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
TABLE 8
Extended Mode Register
Field DLL Bits 0 Type1) w Description DLL Status Enabled 0B 1B Disabled Drive Strength 0B Normal 1B Weak Operating Mode 00000000000BNormal Operation Notes 1. A2 must be 0 to provide compatibility with early DDR devices 2. All other bit combinations are RESERVED.
1) w = write only register bit
DS
1
MODE
[12:3]
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
TABLE 9
Truth Table 1a: Commands
Name (Function) Deselect (NOP) No Operation (NOP) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge (Deactivate Row In Bank Or Banks) Auto Refresh Or Self Refresh (Enter Self Refresh Mode) Mode Register Set
1) 2) 3) 4) 5) 6) 7) 8) 9)
CS H L L L L L L L L
RAS X H L H H H L L L
CAS X H H L L H H L L
WE X H H H L L L H L
Address X X Bank/Row Bank/Col Bank/Col X Code X Op-Code
MNE NOP NOP ACT Read Write BST PRE AR/SR MRS
Note
1)2) 1)2) 1)3) 1)4) 1)4) 1)5) 1)6) 1)7)8) 1)9)
CKE is HIGH for all commands shown exceptSelf Refresh.VREF must be maintained during Self Refresh operation. Deselect and NOP are functionally interchangeable. BA0-BA1 provide bank address and A0-A12 provide row address. BA0, BA1 provide bank address; A0-A9 (x16 device); A0 - A9, A11 (x8 device)provide column address ; A10 HIGH enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts. A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are "Don't Care". This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW. Internal refresh counter controls row and bank addressing; all inputs and I/Os are "Don't Care" except for CKE. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register).
TABLE 10
Truth Table 1b: DM Operation
Name (Function) Write Enable Write Inhibit
1) Used to mask write data; provided coincident with the corresponding data.
DM L H
DQs Valid X
Note
1) 1)
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
TABLE 11
Truth Table 2: Clock Enable (CKE)
Current State CKE n-1 Previous Cycle Self Refresh Self Refresh Power Down Power Down All Banks Idle All Banks Idle Bank(s) Active L L L L H H H H CKEn Current Cycle L H L H L L L H X Deselect or NOP X Deselect or NOP Deselect or NOP AUTO REFRESH Deselect or NOP See Table 12 Maintain Self-Refresh Exit Self-Refresh Maintain Power-Down Exit Power-Down Precharge Power-Down Entry Self Refresh Entry Active Power-Down Entry --
1) 2)
Command n
Action n
Note
1) VREF must be maintained during Self Refresh operation 2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
1. 2. 3. 4.
CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge n. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n. All states and sequences not shown are illegal or reserved.
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
TABLE 12
Truth Table 3: Current State Bank n - Command to Bank n (same bank)
Current State Any Idle CS H L L L L Row Active L L L Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) L L L L L L RAS X H L L L H H L H L H H H L CAS X H H L L L L H L H H L L H WE X H H H L H L L H L L H L L Command Deselect No Operation Active AUTO REFRESH MODE REGISTER SET Read Write Precharge Read Precharge BURST TERMINATE Read Write Precharge Action NOP. Continue previous operation. NOP. Continue previous operation. Select and activate row -- -- Select column and start Read burst Select column and start Write burst Deactivate row in bank(s) Select column and start new Read burst Truncate Read burst, start Precharge BURST TERMINATE Select column and start Read burst Select column and start Write burst Note
1)2)3)4)5)6) 1) to 6) 1) to 6) 1) to 7) 1) to 7)
1) to 6), 8) 1) to 6), 8) 1) to 6), 9) 1) to 6), 8) 1) to 6), 9) 1) to 6), 10)
1) to 6), 8), 11) 1) to 6), 8)
was self refresh). 2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4) The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the "row active" state. Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according to Table 13. 5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM is in the "all banks idle" state. Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM is in the "all banks idle" state. Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state. 6) All states and sequences not shown are illegal or reserved. 7) Not bank-specific; requires that all banks are idle. 8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank. 11) Requires appropriate DM masking.
1) to 6), 9), 11) Truncate Write burst, start Precharge 1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 11 and after tXSNR/tXSRD has been met (if the previous state
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TABLE 13
Truth Table 4: Current State Bank n - Command to Bank m (different bank)
Current State Any Idle CS H L X RAS CAS WE X H X X H X X H X Command Deselect No Operation Any Command Otherwise Allowed to Bank m Active Read Write Precharge Active Read Precharge Active Read Write Precharge Active Read Write Precharge Active Read Write Precharge Action NOP. Continue previous operation. NOP. Continue previous operation. -- Note
1)2)3)4)5)6) 1) to 6) 1) to 6)
Row Activating, Active, or Precharging
L L L L L L L L L L L L L L L
L H H L L H L L H H L L H H L L H H L
H L L H H L H H L L H H L L H H L L H
H H L L H H L H H L L H H L L H H L L
Select and activate row Select column and start Read burst Select column and start Write burst -- Select and activate row Select column and start new Read burst -- Select and activate row Select column and start Read burst Select column and start new Write burst -- Select and activate row Select column and start new Read burst Select column and start Write burst -- Select and activate row Select column and start Read burst Select column and start new Write burst --
1) to 6) 1) to 7) 1) to 7) 1) to 6) 1) to 6) 1) to 7) 1) to 6) 1) to 6) 1) to 8) 1) to 7) 1) to 6) 1) to 6) 1) to 7), 9) 1) to 7), 9), 10) 1) to 6) 1) to 6) 1) to 7), 9) 1) to 7), 9) 1) to 6)
Read (Auto Precharge Disabled) Write (Auto Precharge Disabled)
Read (With Auto Precharge)
Write (With Auto Precharge)
L L L L
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 11: Clock Enable (CKE) and after tXSNR/tXSRD has been met (if the previous state was self refresh). 2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See 10). Write with Auto Precharge Enabled: See 10). 4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle. 5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) All states and sequences not shown are illegal or reserved. 7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8) Requires appropriate DM masking.
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9) Concurrent Auto Precharge:This device supports "Concurrent Auto Precharge". When a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in Table 14. 10) A Write command may be applied after the completion of data output.
TABLE 14
Truth Table 5: Concurrent Auto Precharge
From Command WRITE w/AP To Command (different bank) Read or Read w/AP Write to Write w/AP Precharge or Activate Read w/AP Read or Read w/AP Write or Write w/AP Precharge or Activate Minimum Delay with Concurrent Auto Unit Precharge Support 1 + (BL/2) + tWTR BL/2 1 BL/2 CL (rounded up) + BL/2 1
tCK tCK tCK tCK tCK tCK
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4
4.1
Electrical Characteristics
Operating Conditions
TABLE 15
Absolute Maximum Ratings
This chapter describes the electrical characteristics.
This chapter contains the operating conditions tables.
Parameter
Symbol Min.
Values Typ. -- -- -- -- -- -- 1 50 Max.
Unit
Note/ Test Condition -- -- -- -- -- -- -- --
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT
-0.5 -1 -1 -1 -40 -55 -- --
VDDQ + 0.5
+3.6 +3.6 +3.6 +85 +150 -- --
V V V V C C W mA
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
TABLE 16
Input and Output Capacitances
Parameter Symbol Min. Input Capacitance: CK, CK Delta Input Capacitance Input Capacitance: All other input-only pins Delta Input Capacitance: All other input-only pins Input/Output Capacitance: DQ, DQS, DM Delta Input/Output Capacitance: DQ, DQS, DM CI1 CdI1 CI2 CdIO CIO CdIO 2.0 -- 2.0 -- 4.0 -- Values Typ. -- -- -- -- -- -- Max. 3.0 0.25 3.0 0.5 5.0 0.5 pF pF pF pF pF pF Unit Note/ Test Condition
1) 1) 1) 1) 1)2) 1)
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V 0.2 V, f = 100 MHz, TA = 25 C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground. 2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level.
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
TABLE 17
Electrical Characteristics and DC Operating Conditions
Parameter Symbol Min. Device Supply Voltage Output Supply Voltage Supply Voltage, I/O Supply Voltage Input Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Values Typ. 2.5 2.5 -- 0.5 x VDDQ -- -- -- -- -- -- -- -- -- -- Max. 2.7 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 1.4 2 5 -16.2 -- V V V V V V V V V -- A A mA mA
2) 3)
Unit Note1)/Test Condition
VDD VDDQ VSS, VSSQ VREF VTT
2.3 2.3 0 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 0.71 -2 -5 -- 16.2
VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and VIN(DC)
CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current Input Leakage Current Output Leakage Current
4) 4) 4)
VID(DC) VIRatio II IOZ
4)5)
6)
Any input 0 V VIN VDD; All other pins not under test = 0 V7) DQs are disabled; 0 V VOUT VDDQ 7) VOUT = 1.95 V VOUT = 0.35 V
Output High Current, Normal IOH Strength Driver Output Low Current, Normal IOL Strength Driver
1) -40 C TA 85 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V; 2) Peak to peak AC noise on VREF may not exceed 2% VREF.DC. VREF is also expected to track noise variations in VDDQ. 3) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4) Inputs are not recognized as valid until VREF stabilizes. 5) VID is the magnitude of the difference between the input level on CK and the input level on CK. 6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 7) Values are shown per pin.
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
4.2
AC Characteristics
Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing. Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Figure 2 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level). 6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR SDRAM Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest Industry specification for DDR components.
FIGURE 2
AC Output Load Circuit Diagram / Timing Reference Load
VTT
50 Output (VOUT) Timing Reference Point
30 pF
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
TABLE 18
AC Operating Conditions
Parameter Symbol Min. Input High (Logic 1) Voltage, DQ, DQS and DM Signals Input Low (Logic 0) Voltage, DQ, DQS and DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK Inputs Values Max. -- V V V Unit Note/ Test Condition
1)2)3) 1)2)3) 1)2)3)4)
1)2)3)5) 0.5 x VDDQ- V 0.2 0.2 1) VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR200 - DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400); 0 C TA 70 C
VIH(AC) VIL(AC) VID(AC) VIX(AC)
VREF + 0.31
-- 0.7
VREF - 0.31 VDDQ + 0.6 0.5 x VDDQ+
2) 3) 4) 5)
Input slew rate = 1 V/ns. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The value of VIX is expected to equal 0.5 x VDDQ of the transmitting device and must track variations in the DC level of the same.
TABLE 19
AC Timing - Absolute Specifications for DDR400B and DDR333
Parameter Symbol -5 DDR400B Min. DQ output access time from CK/CK CK high-level width Clock cycle time Max. +0.5 0.55 8 12 12 0.55 -6 DDR333 Min. -0.7 0.45 6 6 7.5 0.45 -- 0.45 1.75 -0.6 0.35 -- -- 0.75 Max. +0.7 0.55 12 12 12 0.55 -- -- -- +0.6 -- ns
2)3)4)5)
Unit
Note1)/ Test Condition
tAC tCH tCK
-0.5 0.45 5 6 7.5
tCK
ns ns ns
2)3)4)5)
CL = 3.0 2)3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5) 2)3)4)5)6)
tCL Auto precharge write recovery tDAL
CK low-level width + precharge time
0.45
(tWR/tCK)+(tRP/tCK) 0.4 1.75 -0.6 0.35 -- -- -- -- +0.6 -- +0.40 +0.40 1.25
tCK tCK
ns ns ns
tDH DQ and DM input pulse width tDIPW
DQ and DM input hold time (each input) DQS output access time from tDQSCK CK/CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (DQS and associated DQ signals)
2)3)4)5) 2)3)4)5)
2)3)4)5)
tDQSL,H tDQSQ
tCK
2)3)4)5)
+0.40 ns +0.45 ns 1.25
TFBGA
2)3)4)5)
TSOPII
2)3)4)5) 2)3)4)5)
Write command to 1st DQS latching transition
tDQSS
0.72
tCK
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
Parameter
Symbol
-5 DDR400B Min. Max. -- -- -- -- +0.7 -- -- -- -- -- +0.70 -- -- +0.50 +0.50 -- 70E+3 -- -- 7.8 -- 1.1 0.60 --
-6 DDR333 Min. 0.45 0.2 0.2 Max. -- -- --
Unit
Note1)/ Test Condition
DQ and DM input setup time DQS falling edge hold time from CK (write cycle)
tDS tDSH
0.4 0.2 0.2 min. (tCL, tCH) -- 0.6 0.7
ns
2)3)4)5) 2)3)4)5)
tCK tCK
ns ns ns ns ns ns ns
DQS falling edge to CK setup tDSS time (write cycle)
2)3)4)5)
tHP Data-out high-impedance time tHZ
Clock Half Period from CK/CK Address and control input hold tIH time
min. (tCL, tCH) -- -- 0.75 0.8 2.2 0.75 0.8 -0.70 2 tHP -tQHS -- -- tRCD 42 60 18 -- 18 0.9 0.40 12 +0.7 -- -- -- -- --
2)3)4)5) 2)3)4)5)7)
fast slew rate
3)4)5)6)8)
slow slew rate3)4)5)6)8)
2)3)4)5)9)
Control and Addr. input pulse tIPW width (each input) Address and control input setup time
2.2 0.6 0.7
tIS
fast slew rate
3)4)5)6)8)
slow slew rate3)4)5)6)8)
2)3)4)5)7)
Data-out low-impedance time tLZ from CK/CK Mode register set command cycle time DQ/DQS output hold time from DQS Data hold skew factor
-0.7 2
+0.70 ns -- --
tMRD tQH tQHS
tCK
ns
2)3)4)5)
tHP -tQHS
-- --
2)3)4)5)
+0.50 ns +0.55 ns -- 70E+ 3 -- -- 7.8 -- 1.1 0.60 -- ns ns ns ns s ns
TFBGA
2)3)4)5)
TSOPII
2)3)4)5) 2)3)4)5) 2)3)4)5)
Active to Autoprecharge delay tRAP Active to Precharge command tRAS Active to Active/Auto-refresh command period Active to Read or Write delay Average Periodic Refresh Interval Precharge command period
tRCD
40 55 15 -- 15 0.9 0.40 10
tRC tRCD tREFI
2)3)4)5)
2)3)4)5) 2)3)4)5)8)
tRP Read preamble tRPRE Read postamble tRPST Active bank A to Active bank B tRRD
command
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tCK tCK
ns
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
Parameter
Symbol
-5 DDR400B Min. Max. -- -- 0.60 -- -- --
-6 DDR333 Min. 0.25 x tCK 0 0.40 15 1 75 200 Max. -- -- 0.60 -- -- -- --
Unit
Note1)/ Test Condition
Write preamble Write preamble setup time Write postamble Write recovery time Internal write to read command delay Exit self-refresh to non-read command
tWPRE tWPRES tWPST tWR tWTR tXSNR
Max. (0.25 x tCK, 1.5 ns) 0 0.40 15 2 75
ns ns
2)3)4)5)
2)3)4)5)10) 2)3)4)5)11) 2)3)4)5) 2)3)4)5)
tCK
ns
tCK
ns
2)3)4)5)
2) Input slew rate 1 V/ns 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 9) These parameters guarantee device timing, but they are not necessarily tested on each device. 10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending on tDQSS. 11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly.
Exit self-refresh to read tXSRD 200 -- command 1) -40 C TA 85 C; VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V
tCK
2)3)4)5)
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
TABLE 20
IDD Conditions
Parameter Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page for detailed test conditions. Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VILMAX; tCK = tCKMIN Symbol
IDD0
IDD1 IDD2P
Precharge Floating Standby Current: CS VIHMIN, all banks idle; IDD2F CKE VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current: CS VIHMIN, all banks idle; CKE VIHMIN; tCK = tCKMIN, address and other control inputs stable at VIHMIN or VILMAX; VIN=VREF for DQ, DQS and DM. Active Power-Down Standby Current: one bank active; power-down mode; CKE VILMAX; tCK= tCKMIN; VIN = VREF for DQ, DQS and DM.
IDD2Q IDD3P
Active Standby Current: one bank active; CS VIHMIN; CKE VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, DM and DQS IDD3N inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3 for DDR333; tCK = tCKMIN; IOUT = 0 mA Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3 for DDR333; tCK = tCKMIN Auto-Refresh Current: tRC = tRFCMIN, burst refresh Self-Refresh Current: CKE 0.2 V; external clock on; tCK = tCKMIN Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test conditions.
IDD4R
IDD4W
IDD5 IDD6 IDD7
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
TABLE 21
IDD Specification
Symbol -6 DDR333 -5 DDR400B 75 90 85 110 4.6 30 23 16 42 45 90 135 95 135 190 5 230 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA x8 2)3) x16 3) x8 3) x16 3)
3) 3) 3) 3)
Unit
Note1)
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
70 85 80 95 4.6 25 22 15 37 40 85 115 90 120 175 5 205
x83) x16 3) x8 3) x16 3) x8 3) x16 3)
3) 4)
x83) x16 3)
230 250 mA 1) Test conditions : VDD = 2.7 V, TA = 10 C 2) IDD specifications are tested after the device is properly initialized and measured at 200 MHz.
3) Input slew rate = 1 V/ns. 4) Enables on-chip refresh and address counters.
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
5
Package Outlines
FIGURE 3
Package Outline PG-TSOPII-66
There is PG-TSOPII-66 package types used for this product family.
Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
List of Figures
Figure 1 Figure 2 Figure 3 Chip Configuration PG-TSOPII-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 AC Output Load Circuit Diagram / Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package Outline PG-TSOPII-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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HYI25DC512[16/80]0CE 512-Mbit Double-Data-Rate SDRAM
List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information for RoHS Compliant Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Chip Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Mode Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Truth Table 1a: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Truth Table 1b: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Truth Table 2: Clock Enable (CKE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Truth Table 3: Current State Bank n - Command to Bank n (same bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Truth Table 4: Current State Bank n - Command to Bank m (different bank). . . . . . . . . . . . . . . . . . . . . . . . . . 16 Truth Table 5: Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Electrical Characteristics and DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AC Timing - Absolute Specifications for DDR400B and DDR333. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Table of Contents
1 1.1 1.2 2 3 4 4.1 4.2 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Chip Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Preliminary Internet Data Sheet
Edition 2006-12 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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